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High-aspect-ratio Ru pillar technology is developed for 0.15 /spl mu/m embedded DRAMs; the cell size is 0.21/spl mu/m/sup 2/. The paper shows the schematic structure of the cell array and the peripheral transistors. The Ru pillars improve the cell performances and logic delay time of the previously proposed pillar DRAM structures. The typical Ta/sub 2/O/sub 5//Ru capacitor shows the equivalent oxide thickness toxeq of 1.1nm and the leakage current of 1nA/cm/sup 2/ at /spl plusmn/O.5V. The Ru pillar is fabricated by etching the sputtered Ru on the CVD-Ru plug. The gate delay of the logic with this embedded DRAM results in smaller than 20% increase of the 0.13 /spl mu/m pure logic without DRAMs. The increase in the contact resistance between Ru and silicon during the 600/spl deg/C annealing to make cell capacitors is effectively suppressed by a barrier metal structure of TiN/Ru.