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A high performance 0.10 /spl mu/m gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10 /spl mu/m-0.13 /spl mu/m gate length with physical 3 nm gate oxides and 0.175 /spl mu/m local interconnect features are optimized for 1.5 V operation to achieve 15 ps unloaded ring oscillator delay. Complementary phase shift masks for superior gate control and low-K dielectrics for reduced coupling capacitance enable an aggressive (>15%) linear shrink of the previous generation copper-based technology. Critical technology layer pitches enable fabrication of 4.5 /spl mu/m/sup 2/ 6T-SRAM cells.
Date of Conference: 6-9 Dec. 1998