By Topic

A high performance 1.5 V, 0.10 /spl mu/m gate length CMOS technology with scaled copper metallization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

31 Author(s)
Gilbert, P. ; Networking & Comput. Syst. Group, Motorola Inc., Austin, TX, USA ; Yang, I. ; Pettinato, C. ; Angyal, M.
more authors

A high performance 0.10 /spl mu/m gate length CMOS technology has been developed with six levels of scaled copper interconnects. Transistors of 0.10 /spl mu/m-0.13 /spl mu/m gate length with physical 3 nm gate oxides and 0.175 /spl mu/m local interconnect features are optimized for 1.5 V operation to achieve 15 ps unloaded ring oscillator delay. Complementary phase shift masks for superior gate control and low-K dielectrics for reduced coupling capacitance enable an aggressive (>15%) linear shrink of the previous generation copper-based technology. Critical technology layer pitches enable fabrication of 4.5 /spl mu/m/sup 2/ 6T-SRAM cells.

Published in:

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Date of Conference:

6-9 Dec. 1998