Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 /spl mu/m CMOS technology for embedded applications

The competing effects of the well (super steep versus uniform channel) and the source/drain (LDD) structures are analyzed on the hot carrier degradation of 90 /spl Aring/, 3.3V I/O transistor integrated on a 0.25 /spl mu/m, 1.8 V technology with a high performance 35 /spl Aring/, 1.8 V core transistor. The cost vs. reliability trade offs in the dual gate oxide integration are discussed.