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Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 /spl mu/m CMOS technology for embedded applications

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11 Author(s)
Bhat, N. ; Networking & Comput. Syst. Group, Motorola Inc., Austin, TX, USA ; Chen, P. ; Tsui, P. ; Das, A.
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The competing effects of the well (super steep versus uniform channel) and the source/drain (LDD) structures are analyzed on the hot carrier degradation of 90 /spl Aring/, 3.3V I/O transistor integrated on a 0.25 /spl mu/m, 1.8 V technology with a high performance 35 /spl Aring/, 1.8 V core transistor. The cost vs. reliability trade offs in the dual gate oxide integration are discussed.

Published in:

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Date of Conference:

6-9 Dec. 1998