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We report a high-performance CMOS operating at 1.5 V with 11.9 ps nominal inverter delay at 0.06/0.08/spl mu/m L/sub eff/ for NMOS and PMOS. Both NMOS and PMOS devices, with 3.6 nm inversion T/sub ox/, have the best current drive reported to date at fixed I/sub off/. Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 9.7 ps inverter delay. These devices are incorporated in a 0.18 /spl mu/m technology that offers a 4.2 /spl mu/m/sup 2/ SRAM cell and dual gate oxide for interfacing to 2.5 V.
Date of Conference: 6-9 Dec. 1998