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Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

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3 Author(s)
H. -S. P. Wong ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; D. J. Frank ; P. M. Solomon

We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.

Published in:

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Date of Conference:

6-9 Dec. 1998