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Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs

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3 Author(s)
Togo, M. ; ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan ; Noda, K. ; Tanigawa, T.

We demonstrate new fabrication technologies for dual-gate CMOSFETs with multiple-thickness gate oxide. The process consists of two major parts: forming a multiple-thickness gate oxide by using Ar/sup +/ and N/sup +/ implantation, and impurity doping into dual-gate poly-Si by using self-aligned thermal oxidation. During the doping process, nitrogen distribution recoiling from a Si/sub 3/N/sub 4/ on a PMOSFET gate suppresses boron penetration.

Published in:

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Date of Conference:

6-9 Dec. 1998