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High performance MCM routing: a new approach

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3 Author(s)
Das, S. ; Dept. of Comput. Sci. & Appl., North Bengal Univ., Darjeeling, India ; Nandy, S.C. ; Bhattacharya, B.B.

In this paper, we present a new approach to MCM routing to minimize the number of vias and wire length. A 3D routing substrate is partitioned into a number of layers. Chip blocks are placed on the top layer, and routing layers are used pair-wise for interconnections. The set of projected pins of the blocks on a routing layer plays the role of obstacles; the space (river) between two consecutive rows/columns of blocks is used for routing. The proposed algorithm consists of a preprocessing stage that determines a routing order among the nets. For each net, a rectilinear Steiner tree with a minimum number of bends is constructed, and the nets are ordered on the basis of a metric called average path length. Next, routing is done in the nonoverlap model, using a heuristic guided by the above ordering. Finally, via minimization is achieved by slightly re-routing the nets in the overlap model. Experimental evidence on standard benchmarks reveals that our solution produces significantly fewer number of vias, and compares favourably with respect to wire length against the best known existing results

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999