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Synthesis of symmetric functions for path-delay fault testability

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4 Author(s)
S. Chakraborty ; Dept. of Comput. Sci., Kalyani Univ., West Bengal, India ; S. Das ; D. K. Das ; B. B. Bhattacharya

A new technique of synthesizing symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit will be 100% robustly path-delay fault testable, if the constituent unate functions are synthesized with two-level irredundant circuits. Non-consecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The hardware overhead of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results reveal that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn reduces testing time as compared to those of the best known earlier methods

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999