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Empirical computation of reject ratio in VLSI testing

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2 Author(s)
S. K. Mehta ; Dept. of Comput. Sci. & Eng., Nebraska Univ., Lincoln, NE, USA ; S. C. Seth

Among significant components of testing cost are test-length, reject ratio, and lost-yield. In this paper a new approach is proposed to estimate the reject ratio. The empirical model is based on test-data properties that are believed to be invariant for a wide range of manufacturing technologies and types of tests. The analysis is carried out entirely in terms of the device test data, as might be available from a wafer probe. Experimental results demonstrate the robustness of the model

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999