By Topic

COST: Circuit Optimization SysTem in ASIC library development environment

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Raghu, C.S. ; ASIC Div., Texas Instrum. (India) Ltd., Bangalore, India ; Bhowmik, S. ; Ramani, P. ; Sundaram, S.

Increased focus on high performance circuit design and shorter development cycle time for ASIC libraries, are driving the need for automatic circuit optimizers in the ASIC library development environment. High performance input/output circuits are the key differentiator cells in the ASIC library market. Automating the design process of these circuits using an optimizer, not only ensures high performance cells but also provides faster design cycle. COST has been used to optimize cells in the development of many ASIC libraries. In this paper we have described the essential components of the COST optimization system and presented a method for optimizing I/O circuits. We have compared the performance of the two cost function heuristics implemented in our optimization system on ASIC input/output circuits

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999