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GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs

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7 Author(s)
B. Basaran ; Design Technol., Intel Corp., Santa Clara, CA, USA ; K. Ganesh ; R. Lau ; A. Levin
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We present a new VLSI layout tool that synthesizes leaf-cell layouts for custom designs as well as standard cell and datapath libraries. GeneSys takes a leaf-cell schematic and a variety of top-down constraints to produce a layout for the circuit. The tool consists of five main components: placer, router, compactor, reliability analyzer and family generator. The system features new 2-D device placement and routing algorithms driven by reliability constraints. A Cell Architecture Rules feature allows customization of the tool to various layout styles. The family generation feature allows rapid synthesis of layout families from template cells. Initial usage statistics show a 2-4X mask designer productivity improvement for a variety of cells

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999