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Optimal voltages and sizing for low power [CMOS VLSI]

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1 Author(s)
Stan, M.R. ; Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA

We provide analytical “back of the envelope” calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999