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Efficient scheduling techniques for ROBDD construction

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3 Author(s)
Murgai, R. ; Fujitsu Labs. of America, Sunnyvale, CA, USA ; Jain, J. ; Fujita, M.

The most common way to build the reduced ordered binary decision diagram (ROBDD) of a complex gate (or function) f of a network is bottom-up, i.e., by first building the ROBDDs of the sub-expressions of f and then suitably combining them. Such a method, however, has been found to suffer from memory explosion, even when the ROBDD of f is not large. This leads to the following fundamental question: Given an arbitrary boolean expression f(x1,x2,...xn ) and the ROBDDs of tts (in terms of circuit inputs), how should the ROBDD of f be constructed so that the intermediate memory repaired to build the ROBDD is minimized, and a heavy time penalty is not incurred? In this paper, we address this question for a restricted f: a multi-way AND or OR operation. We propose various schemes for scheduling the binary operations of the expression f. These schemes are based on an analysis of the sizes and support-sets of the intermediate ROBDDs. One of our main contributions is to prove that under certain conditions, these schemes provide the optimum solution. We tested the proposed schemes on complex functions present within ISCAS85 as well as large industrial circuits. On average, our best scheme (which is based on size as well as support-set of the component ROBDDs) yields a 25% reduction in ROBDD sizes as compared to the technique implemented in SIS [1992]. In some cases. A reduction of up to 4 orders of magnitude was seen. Since ROBDDs are a key technology in various synthesis and verification tasks. Our work can be of immediate use in all these applications

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999