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Improving area efficiency of residue number system based implementation of DSP algorithms

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3 Author(s)
M. N. Mahesh ; Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India ; S. Gupta ; M. Mehendale

Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999