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Formal verification of a snoop-based cache coherence protocol using symbolic model checking

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5 Author(s)
S. Srinivasan ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; P. S. Chhabra ; P. K. Jaini ; A. Aziz
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Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol. Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking. In this paper we present the verification of a three state snoop-based cache coherence protocol using model checking in VIS. As symbolic model checking is beset with the state explosion problem, directly verifying the protocol for a large number of processors is infeasible. We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations. In this paper, we report the techniques we adopted in modeling and verifying the protocol

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999