By Topic

Study of correlation of testability aspects of RTL description and resulting structural implementations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Thaker, P.A. ; Hughes Network Syst. Inc., Germantown, MD, USA ; Zaghloul, M.E. ; Amin, M.B.

RTL-based high level design methodology suffers a major drawback in the area of testability analysis due to lack of effective RTL fault models. Testability of a design is considered structure dependent. Since the structure of a design changes drastically with every logic synthesis run, testability analysis is performed only after final logic synthesis and therefore findings of such effort are too late to be implemented in the design without a significant schedule impact. In this paper we analyze the testability relationship between the RT level design and different structural (gate level) implementations resulting from optimization driven logic synthesis runs. We empirically establish that the testability properties of structural implementations are derived from architectural descriptions at the RT level and therefore logic synthesis does not significantly impact them. Furthermore, various different structural implementations resulting from logic synthesis (with different optimization constraints) exhibit poor testability in the same RTL design space. The data presented in this paper provides a missing key ingredient towards successful RTL fault modeling. We also propose the use of preliminary gate level netlist for early analysis to estimate testability properties of the final implementation

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999