By Topic

Efficient simulation for hierarchical and partitioned circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Maurer, P.M. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA

This paper presents new, highly-efficient techniques for simulating extremely large circuits, assuming that hierarchical design techniques have been used. Both hierarchical and partitioned circuits consist of a master circuit and several sub-circuits. Hierarchical circuits permit sub-circuits to be reused, while partitioned circuits permit only a single use of each sub-circuit. Both types of circuits permit multiple levels of hierarchy. In partitioned circuits, triggering is used to perform simulations that are several times faster than Levelized Compiled Code (LCC) simulation. For hierarchical simulation, the concept of boundary activity is introduced. Optimization with respect to boundary activity can produce simulations that are much faster than ordinary flat simulations. It is further shown that hierarchical design can permit the efficient simulation of circuits that cannot be simulated on a single workstation using ordinary flat simulation. Aggressive use of hierarchy is used to demonstrate the simulation of circuits containing as many as four billion (4,000,000,000) gates

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999