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MPEG-2 video data simulator: a case study in constrained HW-SW codesign

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3 Author(s)
Goswami, R. ; Cadence Design Syst., Noida, India ; Srinivasan, V. ; Balakrishnan, M.

An MPEG-2 video data simulator has been designed in a constrained design space. A hierarchical FSM model has been developed for MPEG-2 video data simulator. This model can be used for any sequence of moving pictures. This model was verified by behavioral (C-language) simulation for a particular case (color-bars data and I I I picture sequence). After an evaluation of the implementation options available in our fairly constrained design space, firmware implementation was selected and implemented

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999

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