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Efficient techniques for reducing IDDQ observation time for sequential circuits

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3 Author(s)
Y. Higami ; Fac. of Eng., Ehime Univ., Matsuyama, Japan ; K. K. Saluja ; K. Kinoshita

In IDDQ testing, long testing time is one of the significant problems, because IDDQ measurement is a time consuming process. In order to reduce the testing time, it is important do reduce the number of IDDQ observation vectors rather than the number of total test vectors. In this paper we, propose efficient techniques to select small number of IDDQ observation vectors. The proposed techniques are use of a concept of essential vectors and concurrent fault simulation. Experimental results for ISCAS '89 benchmark circuits show that the proposed technique reduces the number of IDDQ observation vectors with short computational time

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999