By Topic

An integration of memory-based analog signal generation into current DFT architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hawrysh, E.M. ; Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada ; Roberts, G.W.

One method for the testing of mixed analog/digital integrated circuits involves the digital encoding of analog signals into an aperiodic pulse-density modulated (PDM) serial bit stream and using it to stimulate a device under test (DUT). This paper describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: RAM- and scan-based storage. Using such design-for-test logic as the 1149.1-1990 JTAG architecture and a typical RAMBIST controller, these analog signal generation techniques can be added to digital integrated circuits (IC's) with minimal additional hardware overhead

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:47 ,  Issue: 3 )