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Gate overlap length reduction and shallow junction formation in high-performance fine MOSFETs by ion implantation through thin oxide film

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5 Author(s)
Oishi, T. ; Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan ; Furukawa, A. ; Shiozawa, K. ; Abe, Y.
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A gate overlap length of only 16 nm between the gate and the source/drain has been achieved in fine n-type metal oxide semiconductor field effect transistors with 0.1 μm gate length by arsenic ion implantation through a thin oxide film formed by chemical vapour deposition. The presented technique enables the gate overlap length to be reduced by less than half of the value for conventional lower energy implantation while maintaining a shallow junction depth for the source/drain

Published in:

Electronics Letters  (Volume:34 ,  Issue: 25 )