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A simultaneous placement and global routing algorithm for FPGAs with power optimization

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4 Author(s)
Togawa, Nozomu ; Dept. of Electron., Inf. & Commun. Eng., Waseda Univ., Tokyo, Japan ; Ukai, K. ; Yanagisawa, M. ; Ohtsuki, T.

This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-block. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm

Published in:

Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on

Date of Conference:

24-27 Nov 1998