Learning to knit SOCs profitably

General solutions for SOC (System-on-Chip) test appear to demand new models of partnership among core designers, system integrators, test system manufacturers, test engineers. and process engineers. Each of these partners possesses unique value to contribute to the fundamental understanding that will enable the successful management of the interactions among disparate circuits. Progress towards this goal of cooperation is hastened to the extent that the partners adopt standard practices, which trade off small restrictions in flexibility against large decreases in time to revenue through test. The opportunity before our industry is to identify conditions that allow reasonable semiconductor product performance while also providing a degree of regularity that is sufficient for EDA tools to achieve the required testability. However, the EDA vendors cannot be expected to figure out solutions to all of the problems; they need help from the rest of the industry. Well-supported standards activities provide a means for gleaning lessons from the pioneering visionaries who lead the industry. The potential rewards for those who teach themselves and their partners how to achieve the boldest vision of SOC are tremendous