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Detection of bridging faults in logic resources of configurable FPGAs using IDDQ

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3 Author(s)
L. Zhao ; Lucent Technol., Allentown, PA, USA ; D. M. H. Walker ; F. Lombardi

This paper presents an IDDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100% coverage of IDDQ-testable bridging faults. Since reconfiguration programming time can dominate total test time, even with slow IDDQ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first, and then to minimize the number of test vectors. 100% coverage for IDDQ-testable bridging faults is achieved in 5 programming phases and 16 IDDQ vectors in the Xilinx XC4000 FPGA family. The RAM modes are tested in a further phase, using 48 test vectors and 38 IDDQ measurements

Published in:

Test Conference, 1998. Proceedings., International

Date of Conference:

18-23 Oct 1998