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Compact two-pattern test set generation for combinational and full scan circuits

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2 Author(s)
I. Hamzaoglu ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; J. H. Patel

This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. The test sets generated by MinTest are 30% smaller than the previously published two-pattern test set compaction results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits

Published in:

Test Conference, 1998. Proceedings., International

Date of Conference:

18-23 Oct 1998