Cart (Loading....) | Create Account
Close category search window

Designing for scan test of high performance embedded memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Vida-Torku, E.K. ; Somerset Design Center, IBM Corp., Austin, TX, USA ; Joos, G.

The addressing and clocking schemes in PowerPCTM microprocessor embedded memories present modeling challenges. The ability of most scan based test tools to accurately generate test patterns for these embedded memories is limited. What is needed is aggressive Design for Test implementations that can help the test generation tools. In this paper we present our experiences in the design, modeling, and test of high performance embedded memories on the PowerPC microprocessors

Published in:

Test Conference, 1998. Proceedings., International

Date of Conference:

18-23 Oct 1998

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.