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A high-performance sub-half micron CMOS technology for fast SRAMs

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18 Author(s)
Hayden, J. ; Motorola Inc., Austin, TX, USA ; Baker, F. ; Ernst, S. ; Jones, B.
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An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 125-AA gate oxide, dual n/sup +//p/sup +/ implanted polysilicon gates, titanium salicide, two levels of polysilicon, TiN metallization barriers, a poly plug option, and up to three layers of metallization. An interwell isolation process allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m. Active transistor design is optimized to reduce the polysilicon gate bird's beak and LDD (lightly doped drain) underdiffusion. Discrete transistor lifetimes for hot carrier degradation are in excess of 10 years of 3.3-V operation. A 16 K*4 SRAM displays no parametric shifts after HCl stressing for 1000 h at 7 V and 0 degrees C. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are obtained.<>

Published in:

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Date of Conference:

3-6 Dec. 1989