By Topic

Physical mechanisms for short channel effects in polysilicon thin films transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
A. G. Lewis ; Xerox Palo Alto Res. Center, CA, USA ; T. Y. Huang ; I. -W. Wu ; R. H. Bruce
more authors

It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias. The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes. At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts. Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage. When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves.<>

Published in:

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Date of Conference:

3-6 Dec. 1989