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The paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT including fault ordering, state prediction, and reduced order fault matrix computation, greatly simplify fault simulation by making use of the residual similarities between the faulty and fault free circuits. Between successive time steps, all circuits in the fault list are simulated concurrently before the simulator proceeds to the next time step. CONCERT also generates accurate fault coverage statistics that are tied to the circuit specifications. Up to two orders of magnitudes speedup are obtained for complete fault simulation, without any loss of accuracy. More speedup is achieved by CONCERT for evaluating the fault coverage of a test, using fault ordering and fault dropping technique.