By Topic

On primitive fault test generation in non-scan sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tekumalla, R.C. ; Intel Corp., Hillsboro, OR, USA ; Menon, P.R.

A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses the concept of sensitizing cubes introduced in an earlier paper and a new, more efficient algorithm for generating them. Sensitizing cubes of the next-state and output logic are used to obtain static sensitizing vectors that can be applied to the non-scan sequential circuit as part of a vector-pair. These vector-pairs are also used in deriving robust tests. Initializing sequences from a reset state and sequences that propagate fault effects from flip-flops to primary outputs are also generated. The proposed method has been implemented and used to derive tests for primitive faults in ISCAS'89 and MCNC'91 benchmark circuits.

Published in:

Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on

Date of Conference:

8-12 Nov. 1998