Referenced Items are not available for this document.
We have developed a new parallel processor system specific for the MC analysis, to dramatically reduce the calculation time. Our parallel processor system is based on ring bus architecture. The RISC micro processor chip, which contains a ring bus interface unit (RBIU), a floating point arithmetic unit (FAU) and so on, was also developed for our system. Speed up ratio compared with a single processor reached to 13.5 at 23 PEs.
Published in:
Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on
Date of Conference: 19-21 Oct. 1998
- Page(s):
- 62 - 65
- Meeting Date :
- 19 Oct 1998-21 Oct 1998
- Print ISBN:
- 0-7803-4369-7
- INSPEC Accession Number:
- 6276091
- Conference Location :
- Osaka, Japan
- Digital Object Identifier :
- 10.1109/IWCE.1998.742708
- Product Type:
- Conference Publications
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