An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology

A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<
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