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1/4- mu m LATID (LArge-Tilt-angle Implanted Drain) technology for 3.3-V operation

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1 Author(s)
Hori, T. ; Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

3.3-V operation has been demonstrated for a 1/4- mu m MOSFET having a large-tilt-angle implanted drain (LATID) structure, which is developed by using ultrathin spacers to minimize the n/sup +/ gate overlap while keeping the n/sup -/ region fully overlapped with the gate. The 1/4- mu m LATID device achieves a high saturation transconductance of 200 mu S/ mu m and an excellent propagation delay time of 75 ps/stage (comparable to the device/circuit performance of single-S/D (source/drain) FETs), an improved device lifetime of over 300 years, a low gate-induced drain leakage (GIDL) of less than 0.1 pA/ mu m, and suppressed short-channel effects under 3.3-V operation. It is reconfirmed that the n/sup -/ LAT implant substantially reduces GIDL effects.<>

Published in:

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Date of Conference:

3-6 Dec. 1989