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A diagnostic test generation procedure for combinational circuits based on test elimination

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2 Author(s)
Pomeranz, I. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Fuchs, W.K.

We propose a procedure for generating test patterns for diagnosis of combinational (or fully-scanned sequential) circuits based on stuck-at faults. The test generation procedure avoids the conventional fault-oriented test generation by observing that a test pattern to distinguish two faults can be obtained from a test pattern that detects both of the faults by changing the test pattern so as to “undetect” one of the faults, or change the primary outputs on which the faults are detected. The proposed procedure is applied starting from a fault detection test set (a test set that detects every detectable stuck-at fault). For every pair of faults left undistinguished by the test set, the procedure attempts to modify a test pattern that detects both faults such that the resulting, modified pattern would distinguish the faults. We present experimental results to demonstrate the numbers of fault pairs that can be distinguished by the proposed procedure assuming diagnosis based on full responses and diagnosis based on pass/fail information

Published in:

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

Date of Conference:

2-4 Dec 1998