A new technique to ensure quality of test patterns

This technique detects all active pins in a test pattern electrically using an ATE system. Exhaustive checks on signal pins with different input and output levels ensures that all patterns are stable. Information gathered on active pins for all patterns allows optimised pattern selection for level testing. The technique is portable across different ATE systems and devices. Results show that the test time can be reduced, by up to 31.1% with the proper selection of patterns for level tests of VLSI devices.