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A high-level synthesis method for weakly testable data paths

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5 Author(s)
Inoue, I. ; Nara Inst. of Sci. & Technol., Japan ; Higashimura, T. ; Noda, K. ; Masuzawa, T.
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We present a high-level synthesis method that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for nonscan design. We introduce a design objective for weak testability that is a condition on resource sharing sufficient for weak testability: We propose a heuristic synthesis algorithm that generates a weakly testable data path while minimizing area under a performance constraint

Published in:

Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian

Date of Conference:

2-4 Dec 1998

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