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Neural network congestion controller in prioritised ATM switch

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2 Author(s)
Al-Hammadi, A. ; Dept. of Electron. Eng., Queen Mary & Westfield Coll., London, UK ; Schormans, J.

A neural network (NN) scheme is proposed for congestion control in an ATM switch with time priorities. It is shown that in a prioritised switch it is necessary to monitor the buffer to be controlled as well as buffers with higher priorities. Furthermore, it is shown that the NN scheme in a time prioritised switch gives lower cell loss and delay when compared to the conventional binary scheme

Published in:

Electronics Letters  (Volume:34 ,  Issue: 22 )

Date of Publication:

29 Oct 1998

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