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A planarization technology using a bias-deposited dielectric film and an etch-back process

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4 Author(s)
Fujii, S. ; Semicond. Res. Center, Matsushita Electric Ind. Co. Ltd., Osaka, Japan ; Fukumoto, M. ; Fuse, G. ; Ohzone, T.

A perfect planarization technology with bias deposition of the interlevel dielectric and etch-back process including double photoresist coating has been developed. Firstly, the interlevel SiO2 was deposited by bias sputtering that planarizes only the SiO2 surface on fine aluminum lines. Subsequently, to remove SiO2 plateaus on wide aluminum lines caused by bias deposition, the second planarization by etch-back was performed. Owing to the leveling by the double-layer photoresist coating, a precisely controlled and uniform etch-back was possible, resulting in a nearly planar surface (i.e. the roughness less than ~100 nm) over all device areas on a 6-in wafer. This technology is effective for realizing three or more level submicrometer interconnections in future VLSI systems

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Electron Devices, IEEE Transactions on  (Volume:35 ,  Issue: 11 )