By Topic

A unified approach to statistical design centering of integrated circuits with correlated parameters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Seifi, A. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Ponnambalam, K. ; Vlach, Jiri

This paper presents a general method for statistical design centering of integrated circuits with correlated parameters. It unifies worst-case design, nominal design and tolerance design in a single framework by selecting appropriate norms to measure the distances from the nominal values. The method uses an advanced first-order second moment technique as an alternative to the simplicial algorithm. Yield estimation is calculated in the original space and no transformation to uncorrelated variables is required. The solution algorithms are based on the recently developed interior-point methods for semi-definite programming. One tutorial and one practical example explain the application

Published in:

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:46 ,  Issue: 1 )