A low-cost VLIW DSP architecture for communication equipment

A new DSP architecture based on a traditional VLIW processor is presented. It is able to perform a maximum of 8 instructions per cycle with only a 64-bit instruction word by fetching the address of previously stored instructions instead of the entire instruction word. Simulations have shown that, compared to the VLIW architecture, the reduction of the instruction word size induces no significant decrease of performance in the field of signal processing algorithms. Moreover, in combination with a high-speed external memory, this architecture does not need any instruction cache, making it suitable for applications where low-cost is a key feature.