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Low-power state assignment targeting two- and multilevel logic implementations

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3 Author(s)
Chi-ying Tsui ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, Hong Kong ; Pedram, M. ; Despain, A.M.

The problem of minimizing power consumption during the state encoding of a finite-state machine is addressed. A new power cost model for state encoding is proposed, and encoding techniques that minimize this power cost for two- and multilevel logic implementations are described. These techniques are compared with those that minimize area or the switching activity at the present state bits. Experimental results show significant improvements

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:17 ,  Issue: 12 )

Date of Publication:

Dec 1998

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