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New low-complexity bit-parallel finite field multipliers using weakly dual bases

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3 Author(s)
Huapeng Wu ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Hasan, M.A. ; Blake, I.F.

New structures of bit-parallel weakly dual basis (WDB) multipliers over the binary ground field are proposed. An upper bound on the size complexity of bit-parallel multiplier using an arbitrary generating polynomial is given. When the generating polynomial is an irreducible trinomial xm+xk+1, 1⩽k⩽[m/2], the structure of the proposed bit-parallel multiplier requires only m2 two-input AND gates and at most m2-1 XOR gates. The time delay is no greater than TA+([log2 m]+2)Tx, where TA and TX are the time delays of an AND gate and an XOR gate, respectively

Published in:

Computers, IEEE Transactions on  (Volume:47 ,  Issue: 11 )

Date of Publication:

Nov 1998

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