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Partial-scan delay fault testing of asynchronous circuits

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5 Author(s)
M. Kishinevsky ; Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA ; A. Kondratyev ; L. Lavagno ; A. Saldanha
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Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. Previous work has shown that full-scan delay-fault testing of asynchronous circuits is feasible. In this work, we tackle the problem of partial-scan testing, which requires test-pattern generation on a sequential circuit. We show how this problem can be effectively reduced to a classical problem of stuck-at test-pattern generation for a related combinational circuit. The reduction is done in three steps. The first step reduces testing of an asynchronous sequential circuit, by using a partial-scan approach, to testing an object called an asynchronous net, in which feedback is allowed only inside asynchronous memory elements. We then decompose the problem of testing asynchronous nets into that of initializing memory elements (the second step), followed by robust path delay fault testing (the third step). We provide effective procedures to solve both the initialization and the test-pattern generation problem. The technique is complete, automated, and requires only partial scan of some memory element outputs

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:17 ,  Issue: 11 )