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On-line fault detection for bus-based field programmable gate arrays

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3 Author(s)
Shnidman, N.R. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Mangione-Smith, W.H. ; Potkonjak, M.

We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 4 )