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On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication

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1 Author(s)
Bryant, R.E. ; Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA

Lower-bound results on Boolean-function complexity under two different models are discussed. The first is an abstraction of tradeoffs between chip area and speed in very-large-scale-integrated (VLSI) circuits. The second is the ordered binary decision diagram (OBDD) representation used as a data structure for symbolically representing and manipulating Boolean functions. The lower bounds demonstrate the fundamental limitations of VLSI as an implementation medium, and that of the OBDD as a data structure. It is shown that the same technique used to prove that any VLSI implementation of a single output Boolean function has area-time complexity AT2=Ω(n 2) also proves that any OBDD representation of the function has Ω(cn) vertices for some c>1 but that the converse is not true. An integer multiplier for word size n with outputs numbered 0 (least significant) through 2n-1 (most significant) is described. For the Boolean function representing either output i-1 or output 2n-i-1, where 1⩽in, the following lower bounds are proved: any VLSI implementation must have AT 2=Ω(i2) and any OBDD representation must have Ω(1.09i) vertices

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Computers, IEEE Transactions on  (Volume:40 ,  Issue: 2 )