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A cost-effective architecture for HDTV video decoder in ATSC receivers

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2 Author(s)
Jeong-Min Kim ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Soo-Ik Chae

We describe the architecture of an HDTV video decoder, Vincent5, for MPEG2 MP@HL video decoding and format conversion of all 18 ATSC DTV formats in real-time. Vincent5 adopts a dataflow architecture for its main decoding functions in contrast to the conventional decoders that use a strict pipelined structure. Consequently, this makes it possible for us to explore wide design choices in the architecture decision for each decoding function. In Vincent5 we introduce a new memory control scheme of reducing the memory bandwidth, which is necessary in MPEG2 MP@HL decoding for a cost-effective solution. Without increasing the hardware complexity of Vincent5, we embed three programmable cores into the dedicated hardware to maximize its programmability. Vincent5 was described using the VHDL and its functionality was verified with standard MPEG2 bitstreams. Vincent5 includes 115 K logic gates, 118 Kb RAM, and 32 Kb ROM after logic synthesis and had been fabricated utilizing 3 ML 0.5 μm CMOS technology

Published in:

IEEE Transactions on Consumer Electronics  (Volume:44 ,  Issue: 4 )