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A compact LDD MOSFET I-V model based on nonpinned surface potential

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3 Author(s)
Sheng-Lyang Jang ; Dept. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shau-Shen Liu ; Chorng-Jye Sheu

Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data

Published in:

Electron Devices, IEEE Transactions on  (Volume:45 ,  Issue: 12 )