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Enhancement-mode high electron mobility transistors (E-HEMTs) lattice-matched to InP

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5 Author(s)
Mahajan, A. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Arafa, Mohamed ; Fay, P. ; Caneau, C.
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The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 μm. A maximum extrinsic transconductance (gmext) of 701 mS/mm and a threshold voltage (VT) of 167 mV was measured for 0.3 μm gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f t) of 116 GHz was measured as well as a maximum frequency of oscillation (fmax) of 229 GHz for 0.3 μm gate-length E-HEMTs

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Electron Devices, IEEE Transactions on  (Volume:45 ,  Issue: 12 )