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Low-power dividerless frequency synthesis using aperture phase detection

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11 Author(s)
Shahani, A.R. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Shaeffer, D.K. ; Mohan, S.S. ; Samavati, H.
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A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLL's loop bandwidth is measured to he 6 MHz, with a reference spurious level of -47 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5-μm, triple-metal, single-poly CMOS process and operates on a 2.5-V supply

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Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 12 )